1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a clock synchronous semiconductor memory device for taking in data and a signal applied externally in synchronization with a clock signal. More specifically, the present invention relates to a circuit arrangement for adjusting a data take-in timing of the clock synchronous semiconductor memory device.
2. Description of the Background Art
FIG. 25 is a schematic diagram representing an overall configuration of a conventional semiconductor memory device. In FIG. 25, a semiconductor memory device 900 includes a memory circuit 902 having a plurality of memory cells, a clock buffer 904 for generating an internal clock signal according to a clock signal CLK applied externally, a main control circuit 906 for taking in an externally applied command CMD in synchronization with the internal clock signal generated from clock buffer 904 and generating a variety of control signals required for an operating mode designated by this command, an input/output circuit 910 for transferring data between memory circuit 902 and an external device, and an input/output control circuit 908 for controlling the data input/output operation of input/output circuit 910 under the control of main control circuit 906.
Memory circuit 902 includes a plurality of memory cells arranged in a matrix of rows and columns, a memory cell selecting circuit for selecting a row and a column of memory cells according to an address signal ADD under the control of main control circuit 906, and a write/read circuit for transferring internal data with input/output circuit 910. The memory cell selecting circuit and the write/read circuit are activated in a prescribed sequence under the control of main control circuit 906.
Input/output control circuit 908 controls an external data input operation of input/output circuit 910 according to an externally supplied data strobe signal DQS in a data write operation. In a data output operation, input/output control circuit 908 outputs data strobe signal DQS in synchronization with the data output. Input/output circuit 910 outputs data in synchronization with the internal clock signal in data output operation.
Thus, data strobe signal DQS provides a data take-in timing in the semiconductor memory device in the data write operation, and provides a data take-in timing in an external controller or processor in the data output operation.
Main control circuit 906 decodes an externally supplied command CMD at a rising edge of the internal clock signal generated from clock buffer 904 and generates a variety of control signals necessary for performing the operating mode designated by command CMD. Command CMD includes a plurality of control signals and a specific address signal bit. A command for instructing one operating mode is formed by a combination of logic levels of these signals at the rising edge of clock signal CLK.
FIG. 26 is a schematic diagram representing an arrangement of a data input circuit for one bit of input/output circuit 910 shown in FIG. 25. In FIG. 26, the data input circuit includes a latch circuit 920 for taking in and latching externally supplied data DIN in response to the rise of data strobe signal DQS, a latch circuit 921 for taking in and latching data DIN from outside in response to the fall of data strobe signal DQS, a latch circuit 922 for taking in and latching latch data DILF0 of latch circuit 920 according to a transfer instructing signal DQSDT, a latch circuit 923 for taking in and latching latch data DILF1 of latch circuit 921 according to transfer instructing signal DQSDT, a register circuit 924 for taking in and latching latch data DIL0 of latch circuit 922 in response to a latch transfer instructing signal ZLTTR, and a register circuit 925 for taking in and latching latch data DIL1 of latch circuit 923 according to latch transfer instructing signal ZLTTR.
Transfer instructing signal DQSDT is generated in the form of a one-shot pulse in response to the fall of data strobe signal DQS.
Latch transfer instructing signal ZLTTR is generated in the form of a one-shot pulse in synchronization with the rise of the internal clock signal in the data write operation. The latch data of register circuits 924 and 925 are transferred in parallel to an internal data bus.
In the internal data bus, an even-numbered data bus corresponding to an even-numbered data address and an odd-numbered data bus corresponding to an odd-numbered data address are provided, and the latch data of register circuits 924 and 925 are transferred to these even-/odd-numbered data buses according to a column address signal.
FIG. 27 is a timing chart representing an operation of the data input circuit shown in FIG. 26. The operation of the data input circuit shown in FIG. 26 will be described briefly below with reference to FIG. 27.
In a data write operation, data strobe signal DQS is input in synchronization with clock signal CLK, and write data DIN is input in synchronization with data strobe signal DQS.
Latch circuit 920 takes in and latches external data DIN in response to the rise of data strobe signal DQS, and generates internal latch data DILF0. Latch circuit 921 takes in external data DIN in response to the fall of data strobe signal DQS and generates internal latch data DILF1. In the data write operation, transfer instructing signal DQSDT is generated in the form of a one-shot pulse in response to the fall of data strobe signal DQS, and latch circuits 922 and 923 take-in and latch the latch data DILF0 and DILF1 of latch circuits 920 and 921, respectively.
Then, latch transfer instructing signal ZLTTR is generated in the form of a one-shot pulse in response to the rise of clock signal CLK, and register circuits 924 and 925 take in and latch the latch data DIL0 and DIL1 of latch circuits 922 and 923, respectively.
Thus, by internally converting data DIN transferred externally in synchronization with the rising edge and the falling edge of data strobe signals DQS into parallel data, and thereafter, by internally transferring the converted data in parallel according to latch transfer instructing signal ZLTTR in synchronization with clock signal CLK, the valid period width of internal data DIL0 and DIL1 can be made equal to one clock cycle period of clock signal CLK, thereby achieving a greater effective valid data width.
Memory circuit 902 operates in synchronization with the internal clock signal, and by performing the above-described processing of the data transferred in synchronization with both the rising edge and the falling edge of data strobe signal DQS, the processing (writing/reading) can be performed with one of the edges of clock signal CLK used as a trigger.
The method of employing data strobe signal DQS to take in the data is called a source synchronous scheme. By transferring the data strobe signal via the same path as the data transfer path, even when the delay time of the data transferred from a controller with respect to the clock signal from a clock generating circuit increases to decrease the valid data width, data can be reliably taken into the semiconductor memory device.
The scheme of transferring data in synchronization with both the rising edge and the falling edge of a clock signal is called the DDR (Double Data Rate) mode. The data transferred serially is taken in, latch transfer instructing signal ZLTTR is generated in synchronization with clock signal CLK internally, and the parallel internal write data is generated in synchronization, for instance, with the rising edge of the internal clock signal. In the memory circuit, the writing and reading process can be performed with a sufficient margin with one of the edges of the clock signal used as a trigger. Thus, data can be transferred at a high speed in synchronization with a high-speed clock signal, the data bandwidth can be increased, and the processing efficiency of the system can be improved.
FIG. 28 is a diagram representing an example of an arrangement of a conventional processing system. In FIG. 28, four memories MD0 to MD3 are provided for a controller CLT. These memories MD0 to MD3 can each be a one-chip memory device or a memory module.
A clock signal CLK from a clock generating circuit CGEN is applied in common to controller CLT and these memories MD0 to MD3. Controller CTL generates and transfers a data strobe signal DQS, a command CMD, and write data DQ to memories MD0 to MD3 in a data write operation according to clock signal CLK from the clock generating circuit CGEN. Each of memories MD0 to MD3 operates in synchronization with clock signal CLK from clock generating circuit CGEN supplied to a clock input CK.
In the case of the arrangement of the processing system shown in FIG. 28, the respective distances between controller CTL and memories MD0 to MD3 differ from each other. Thus, when clock signal CLK is generated from clock generating circuit CGEN and the propagation time (flight time) of the data from controller CTL becomes long, the phase difference between clock signal CLK and data strobe signal DQS becomes great.
FIG. 29 is a timing chart representing a data write operation of the processing system shown in FIG. 28. FIG. 29 shows an operation in the case in which the burst length is four and four data are written successively with one write command.
Memory MD0 is closest to controller CTL, while memory MD3 is farthest from controller CTL. The delay of data strobe signal DQS from controller CTL with respect to clock signal CLK becomes the greatest in memory MD3.
A write command instructing a data write (denoted by a signal /WE) is supplied as command CMD, and then, data strobe signal DQS is transferred in synchronization with clock signal CLK. As a phase shift of data strobe signal DQS with respect to clock signal CLK, a phase difference of +25% is allowed, for instance.
Therefore, in memory MD0, in the case when a phase difference of xc2xc cycle, for instance, exists between clock signal CLK and data strobe signal DQS, when latch transfer instructing signal ZLTTR is generated in response to the rise of clock signal CLK, there is a possibility that adequate hold time for data DIL0 and DIL1 may not be ensured and an accurate internal data transfer cannot be performed.
In memory MD1, the phases of clock signal CLK and data strobe signal DQS substantially coincide with each other, and the internal data can be generated with accuracy according to latch transfer instructing signal ZLTTR for data DIL0 and DIL1. In addition, also in memory MD2, the phase difference of data strobe signal DQS with respect to clock signal CLK is small, and thus, sufficient set up time and hold time of data DIL0 and DIL1 relative to latch transfer instructing signal ZLTTR can be ensured, and the internal data can be generated with accuracy.
In memory MD3, further, data strobe signal DQS is delayed, and the transmission of data DQ is also delayed so that, when latch transfer instructing signal ZLTTR is generated in synchronization with the rise of clock signal CLK, there is a possibility that adequate set up time for data DIL0 and DIL1 cannot be ensured and accurate internal write data cannot be generated.
Here, a write command is allocated with a sufficiently long period for its active state period as indicated by the broken line in FIG. 29, and a skew of the write command relative to clock signal CLK does not affect the command decode operation in memories MD0 to MD3. Thus, the command CMD is decoded accurately and it is determined that the write command is supplied.
As shown in FIG. 29, in the case in which the burst length is four and data D0 to D3 are successively transferred according to one write command, since the transfer time periods of the data and the data strobe signal differ according to the distances between the memories and the controller, the phase differences relative to clock signal CLK differ. Therefore, a possibility arises that the internal data cannot be generated accurately according to the latch transfer instructing signal.
Moreover, in the case where clock signal CLK at an even higher speed is employed, since the propagation delay time (flight time) of the data propagation path in the processing system is the same, the ratio of the phase difference within the clock cycle time becomes greater as the difference 25. between the flight time and the clock cycle time is reduced.
Now, a situation is considered in which the phase of data strobe signal DQS is advanced by a half cycle relative to clock signal CLK as shown in FIG. 30. In this case, a write command is supplied (a write enable signal /WE is set to the logic low or L level), and then, in that clock cycle #0, data strobe signal DQS rises to the logic high or H level, data D0 is taken into a memory, and latch data DIL0 changes to data D0. Thereafter, when data strobe signal DQS falls, latch data DIL0 and DIL1 are provided by data DO and D1 according to the external data.
Latch transfer instructing signal ZLTTR is generated when two clock cycles have passed since the write command is supplied so that the latch transfer instructing signal is in the inactive state in clock cycle #1, and latch transfer instructing signal ZLTTR attains the active state in clock cycle #2. In clock cycle #2, data D2 and D3 are latched as latch data DIL0 and DIL1, and the latch/transfer operation of the first two data D0 and D1 is not performed.
As shown in FIG. 30, if time tDQSS from the supply of the write command to the rise of data strobe signal DQS becomes short beyond a permitted value, a problem arises in that the initial transferred data cannot be taken in.
In addition, when latch transfer instructing signal ZLTTR is activated in clock cycle #2, if the set up time of latch data DIL0 and DIL1 (D2, D3) is insufficient, accurate internal write data cannot be generated.
Moreover, the case is considered in which data strobe signal DQS is generated with a further delay beyond clock signal CLK, as shown in FIG. 31. In this case, the flight time of data strobe signal DQS is long, and data strobe signal DQS attains the H level in the next clock cycle #1 after the write command is supplied. In other words, the situation in which time tDQSS becomes long is considered.
In this situation, data strobe signal DQS and data DQ are transferred in the same direction, and data DQ is taken in according to the rising edge and the falling edge of data strobe signal DQS, and latch data DILF0, DIL0, and DIL1 are generated. Since latch data DIL0 and DIL1 are generated in response to the fall of data strobe signal DQS, latch data DIL0 and DIL1 are invalid data in clock cycle #1.
In clock cycle #2, latch transfer instructing signal ZLTTR is activated so that internal write data is generated according to data D0 and D1. In this case, also, the set up time of latch data DIL0 and DIL1 relative to latch transfer instructing signal ZLTTR is insufficient so that there is a possibility that the internal write data cannot be generated with stability.
In addition, as shown in FIGS. 30 and 31, since latch transfer instructing signal ZLTTR is activated when a second clock cycle elapses since the write command is supplied, the data in clock cycle #2 differ depending on the phase relation of data strobe signal DQS with clock signal CLK, and the problem arises that the internal write data cannot be accurately generated. In particular, when write commands are successively supplied to write data, it becomes impossible to identify whether the data latched according to the latch transfer instructing signal is the data according to the first write command or the data according to the next write command, and the problem arises that the data write operation cannot be performed accurately according to the position of the memory from the controller.
Moreover, in order accurately to set the data take-in timing, data strobe signal DQS is held at the L level for a prescribed period of time prior to the data writing. The period during which data strobe signal DQS is at the L level is called a preamble.
Thus, in FIG. 32, when issuing a write command, the controller temporarily sets to the L level the data strobe signal DQS that had been held in a high impedance state or at an intermediate voltage level, and thereafter, raises data strobe signal DQS to the H level in synchronization with clock signal CLK.
By prolonging the preamble portion in which data strobe signal DQS is at the L level to one clock cycle period, even in the case where the flight time becomes long, it is possible to identify the starting point of the rise of data strobe signal DQS, i.e., the starting point of data take-in operation. The preamble portion is similarly transmitted along with the propagation of data strobe signal DQS. When such preamble portion of data strobe signal DQS is set to, for instance, one clock cycle period, a memory remote from the controller does not take in the data during this preamble period, and thus, the data take-in timing is delayed. Therefore, when the data write operation is performed for different memories, the writing of data is never performed during this preamble period, and therefore, a problem arises in that the data write operation cannot be performed at a high speed.
In addition, also in the case where the preamble period is made long, the timing at which the preamble period is detected varies among the memories so that the preamble portion of the data strobe signal cannot be accurately detected.
When a clock signal is transferred from the controller to a memory, the flight time of the clock signal becomes equal to the flight time of write data and the data strobe signal so that it might be possible to take in the data in each of the memories without being affected by the flight time of the data. The clock signal, however, is transmitted from the controller to the memories commonly via an on-board wiring line so that there is a need to increase the drivability of the portion for transmitting the clock signal in the controller. The area occupied by the controller becomes larger and the power consumption for generating the clock signal in the controller also increases. Thus, an oscillator such as a crystal oscillator, separate from these memories and the controller, is arranged for generating a clock signal with a large driving power and with accuracy by so as to generate a common system clock for the controller and the memories. Therefore, the problem of the phase differences between the clock signal and the data and between a clock signal and a data strobe signal varying according to the respective distances between the memories and the controller always occurs in an onboard assembled system. In particular, when a high speed clock signal is employed, the flight time and the clock cycle period becomes substantially the same length so that the problem arises that the internal data cannot be accurately transferred in a memory.
An object of the present invention is to provide a semiconductor memory device capable of accurately performing take-in of data and generation of internal write data in synchronization with a high speed clock signal.
Another object of the present invention is to provide a semiconductor memory device capable of performing take-in of data and generation of internal write data in synchronization with a high speed clock signal with accuracy regardless of the distance from the controller.
A semiconductor memory device according to the present invention includes a position information generating circuit for generating position information indicating a position on the basis of a controller, a data take-in instructing signal generating circuit for adjusting a timing for taking in data supplied from the controller to generate a data take-in instructing signal according to the position information generated from the position information generating circuit and a write instructing signal supplied from the controller, and a write circuit for generating internal data corresponding to the data from the controller according to the data take-in instructing signal.
In the semiconductor memory device, by setting the position information according to the distance relative to the controller and by adjusting the timing for generating the internal write data according to the position information, data can be taken in with accuracy even when the flight time of a signal/data differs according to the position on the basis of the controller. Consequently, in the case where data transfer is performed using a high speed clock signal, the data can be taken in and the internal write data can be generated with accuracy even when the flight time of a signal/data is substantially the same as one clock cycle period of a clock signal.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.